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CAT24C00
128-bit Serial EEPROM FEATURES
I 400 kHz I2C bus compatible* I 1.8 to 5.5 volt operation I Low power CMOS technology I Self-timed write cycle with auto-clear I 1,000,000 Program/erase cycles I 100 year data retention
H
GEN FR ALO
EE
LE
A D F R E ETM
I 8-pin DIP, 8-pin SOIC, 8 pin TSSOP and SOT-23 I Industrial and Extended Temperature Ranges
DESCRIPTION
The CAT24C00 is a 128-bit Serial CMOS EEPROM internally organized as 16 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The device operates via the I2C bus serial interface and is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 5-pin SOT-23.
PIN CONFIGURATION
DIP Package (P, L)
NC NC NC VSS 1 2 3 4 8 7 6 5 VCC NC SCL SDA
BLOCK DIAGRAM
SOIC Package (J, W)
EXTERNAL LOAD
NC NC NC VSS 1 2 3 4 8 7 6 5 VCC NC SCL SDA
DOUT ACK VCC VSS WORD ADDRESS BUFFERS
SENSE AMPS SHIFT REGISTERS
COLUMN DECODERS
SOT-23 (TP, TB)
SCL VSS SDA 1 2 3 4 NC 5 VCC
TSSOP Package (U, Y)
SDA
NC NC NC VSS
1 2 3 4
8 7 6 5
VCC NC SCL SDA
START/STOP LOGIC
XDEC CONTROL LOGIC
E2PROM
PIN FUNCTIONS
Pin Name SDA SCL NC VCC VSS Function Serial Data/Address Serial Clock No Connect 1.8 V to 5.5 V Power Supply Ground
SCL STATE COUNTERS HIGH VOLTAGE/ TIMING CONTROL DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
(c) 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1027, Rev. N
CAT24C00
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(1) ............ -2.0 V to VCC + 2.0 V VCC with Respect to Ground ............. -2.0 V to +7.0 V Package Power Dissipation Capability (TA = 25C) .................................. 1.0 W Lead Soldering Temperature (10 seconds) ...... 300C Output Short Circuit Current(2) ....................... 100 mA RELIABILITY CHARACTERISTICS Symbol NEND VZAP
(3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
Min 1,000,000 100 2000 100
Typ
Max
Units Cycles/Byte Years Volts mA
TDR(3)
(3)
ILTH(3)(4)
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, unless otherwise specified.
Symbol ICC ISB
(5)
Parameter Power Supply Current Standby Current (VCC = 5.0 V) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0 V) Output Low Voltage (VCC = 1.8 V)
Test Conditions fSCL = 400 kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC
Min
Typ
Max 2 1 10 10
Units mA A A A V V V V
ILI ILO VIL VIH VOL1 VOL2
-1 VCC x 0.7 IOL = 3 mA IOL = 1.5 mA
VCC x 0.3 VCC + 0.5 0.4 0.5
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5 V Symbol CI/O(3) CIN(3) Parameter Input/Output Capacitance (SDA) Input Capacitance (SCL) Test Conditions VI/O = 0 V VIN = 0 V Min Typ Max 8 6 Units pF pF
Note: (1) The minimum DC input voltage is - 0.5 V. During transitions, inputs may undershoot to - 2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from - 1 V to VCC + 1 V. (5) Maximum standby current (ISB) = 10A for the Extended Automotive temperature range.
Doc. No. 1027, Rev. N
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CAT24C00
A.C. CHARACTERISTICS
VCC = 1.8 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits Symbol Parameter 1.8 V - 6.0 V Min FSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF
(1)
2.5 V - 6.0 V Min Max 400 100 1 1.2 0.6 1.2 0.6 0.6 0 50 Units kHz ns s s s s s s ns ns 0.3 300 0.6 100 s ns s ns
Max 100 100 3.5
Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time 4 100 4.7 4 4.7 4 4.7 0 50
1 300
tSU:STO tDH
Power-Up Timing(1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Typ Max 1 1 Units ms ms
Write Cycle Limits Symbol tWR Parameter Write Cycle Time Min Typ Max 5 Units ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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Doc. No. 1027, Rev. N
CAT24C00
FUNCTIONAL DESCRIPTION
The CAT24C00 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24C00 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master device controls which mode is activated.
SDA: Serial Data/Address The CAT24C00 bidirectional serial data/address pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs.
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.
PIN DESCRIPTIONS
SCL: Serial Clock The CAT24C00 serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. Figure 1. Bus Timing tF
tLOW SCL tSU:STA tHD:STA tHD:DAT tHIGH tLOW
tR
tSU:DAT
tSU:STO
SDA IN tAA SDA OUT
5020 FHD F03
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
Doc. No. 1027, Rev. N
STOP BIT
4
CAT24C00
START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24C00 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.
The CAT24C00 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. When the CAT24C00 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24C00 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 for the CAT24C00 (see Fig. 5). The next three significant bits are "don't care" bits. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24C00 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24C00 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. Figure 4. Acknowledge Timing
WRITE OPERATION
Byte Write In the Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends the byte address that is to be written into the address pointer of the CAT24C00. After receiving another acknowledge from the Slave, the Master device transmits the data byte to be written into the addressed memory location. The CAT24C00 acknowledges once more and the Master generates the STOP condition, at which time the device begins its internal programming cycle to nonvolatile memory. While this internal cycle is in progress, the device will not respond to any request from the Master device. After a write command, the internal address counter will continue to point to the same address location that was just written. If a stop bit is transmitted to the device at any point in the write sequence before the entire sequence is complete, then the command will abort and no data will be written. If more than eight
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
5020 FHD F06
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CAT24C00
Figure 5. Slave Address Bits
CAT24C00
1
0
1
0
X
X
X
R/W
bits are transmitted before the stop bit is sent, then the device will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a stop bit is sent before a full eight bits of data have been transmitted, then the write command will abort and no data will be written. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT24C00 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the CAT24C00 is still busy with the write operation, no ACK will be returned. If the CAT24C00 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a `dummy' write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24C00 acknowledges the word address, the Master device resends the START condition and the slave address, this time with the R/W bit is set to one. The CAT24C00 then responds with its acknowledge and sends the 8-bit byte requested. To end the Read Operation the master device does not send an acknowledge but will generate a STOP condition.
Sequential Read The Sequential READ operation can be initiated by either the immediate Address READ or Selective READ operations. After the CAT24C00 sends initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24C00 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation is terminated when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT24C00 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24C00 address bits so that the entire memory array can be read during one operation. If more than 16 bytes are read out, the counter will "wrap around" and continue to clock out data bytes.
READ OPERATIONS
The READ operation for the CAT24C00 is initiated in the same manner as the write operation with the one exception that the R/W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The device's address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ access was to address N, the READ immediately following would access data from address N+1. If N=15, then the counter will 'wrap around' to address 0 and continue to clock out data.
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CAT24C00
Figure 6. Byte Write Timing
S T A R T S A C K A C K A C K
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS
DATA
S T O P P
Figure 7. Immediate Address Read Timing
S T BUS ACTIVITY: A MASTER R T SDA LINE S A C K DATA N O A C K S T O P P
SLAVE ADDRESS
SCL
8
9
SDA
8TH BIT DATA OUT NO ACK STOP
Figure 8. Selective Read Timing
S T A R T S A C K A C K S T A R T S A C K DATA n N O A C K S T O P P
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS (n)
SLAVE ADDRESS
Figure 9. Sequential Read Timing
BUS ACTIVITY: MASTER SDA LINE A C K A C K A C K A C K N O A C K SLAVE ADDRESS S T O P P
DATA n
DATA n+1
DATA n+2
DATA n+x
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CAT24C00
ORDERING INFORMATION
Prefix CAT Device # 24C00 Suffix J I X TE13 Rev B(2)
Optional Company ID
Product Number 24C00: 128 Bit
Temperature Range I = Industrial (-40 to 85 C) E = Extended (-40 to 125 C)
Tape & Reel TE13: 2000/Reel
Package P: PDIP J : SOIC (JEDEC) U: TSSOP TP: SOT23 L : PDIP (Lead free, Halogen free) TB: SOT23 (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free)
Operating Voltage Blank: 1.8 V - 5.5 V
Die Revision
Notes: (1) The device used in the above example is a CAT24C00JI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWB). For additional information, please contact your Catalyst sales office.
Doc. No. 1027, Rev. N
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CAT24C00
REVISION HISTORY
Date 9/24/2003 10/30/2003 12/9/2003 12/23/2003 12/29/2003 Rev. H I J K L Reason Eliminated commercial temperature range class Updated marking Eliminated automotive temperature reange Changed Industrial temp range designation from "Blank" to "I" Eliminatd Commercial and Automotive temp ranges from Features on front page of data sheet Moved DC Operating Characteristics typ numbers for VOL1 and VOL2 to max column Changed 1.8V to 1.8V - 6.0V for AC Characteristics Changed 4.5V - 5.5V to 2.5V - 6.0V for AC Characteristics 7/7/2004 7/27/2004 M N Added Die Revision to Ordering Information Updated DC Operating Characteristics chart and notes
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CAT24C00
Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM AE2 TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com
Doc. No. 1027, Rev. N
Publication #: Revison: Issue date:
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1027 N 7/27/04

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